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KSZ8041TL/ftl 10base-t/100base-tx/100base-fx physical layer transceiver data sheet rev. 1.1 linkmd is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com april 2007 m9999-042707-1.1 general description the KSZ8041TL is a single supply 10base-t/100base-tx physical layer transceiver, which provides mii/rmii/smii interfaces to transmit and receive data. it utilizes a unique mixed-signal design to extend signaling distance while reducing power consumption. hp auto mdi/mdi-x provides the most robust solution for eliminating the need to differentiate between crossover and straight-through cables. micrel linkmd ? tdr-based cable diagnostics permit identification of faulty copper cabling. the KSZ8041TL represents a new level of features and performance and is an ideal choice of physical layer transceiver for 10base-t/1 00base-tx applications. the ksz8041ftl has all the identical rich features of the KSZ8041TL plus 100base-fx support for fiber and media converter applications. both KSZ8041TL and ksz8041ftl are available in 48- pin, lead-free tqfp packages (see ordering information). data sheets and support documentation can be found on micrel?s web site at: www.micrel.com. functional diagram
micrel, inc. KSZ8041TL/ftl april 2007 2 m9999-042707-1.1 features ? single-chip 10base-t/100base-tx physical layer solution ? fully compliant to ieee 802.3u standard ? low power cmos design, power consumption of <180mw ? hp auto mdi/mdi-x for reliable detection and correction for straight-through and crossover cables with disable and enable option ? robust operation over standard cables ? linkmd ? tdr-based cable diagnostics for identification of faulty copper cabling ? fiber support: 100base-fx (ksz8041ftl only), back- to-back mode (ksz8041ftl and KSZ8041TL) ? mii interface support ? rmii interface support with external 50mhz system clock ? smii interface support with external 125mhz system clock and 12.5mhz sync clock from mac ? miim (mdc/mdio) management bus to 12.5mhz for rapid phy register configuration ? interrupt pin option ? programmable led outputs for link, activity and speed ? power down and power saving modes ? single power supply (3.3v) ? built-in 1.8v regulator for core ? available in 48-pin tqfp package applications ? printer ? lom ? game console ? iptv ? ip phone ? ip set-top box ? media converter ordering information part number temp. range package lead finish KSZ8041TL 0c to 70c 48-pin tqfp pb-free KSZ8041TLi (1) -40c to 85c 48-pin tqfp pb-free ksz8041ftl 0c to 70c 48-pin tqfp pb-free ksz8041ftli (1) -40c to 85c 48-pin tqfp pb-free note: 1. contact factory for lead time.
micrel, inc. KSZ8041TL/ftl april 2007 3 m9999-042707-1.1 revision history revision date summary of changes 1.0 12/21/06 data sheet created. 1.1 4/27/07 added maximum mdc clock speed. added 40k +/-30% to note 1 of pin description and strapping options tables for internal pull-ups/pull- downs. changed model number in register 3h ? phy identifier 2. changed polarity (swapped definition) of duplex strapping pin. removed duplex strapping pin update to register 4h ? auto-negotiation advertisement bits [8, 6]. added back-to-back mode for KSZ8041TL. added symbol error to mii/rmii receive erro r description and register 15h ? rxer counter. added a 100pf capacitor on rext (p in 16) in pin description table.
micrel, inc. KSZ8041TL/ftl april 2007 4 m9999-042707-1.1 contents pin confi guration .............................................................................................................. .................................................... 8 pin descr iption ................................................................................................................ .................................................... 10 strapping options.............................................................................................................. ................................................. 15 functional d escripti on ......................................................................................................... .............................................. 17 100base-tx transm it............................................................................................................ ........................................... 17 100base-tx receive............................................................................................................. ........................................... 17 pll clock synthesizer.......................................................................................................... ............................................ 17 scrambler/de-scrambler (100base-tx only)....................................................................................... ............................. 17 10base-t tr ansmit .............................................................................................................. ............................................. 17 10base-t re ceive ............................................................................................................... ............................................. 18 sqe and jabber function (10base-t only)........................................................................................ .............................. 18 auto-negot iation ............................................................................................................... ................................................ 18 mii management (miim ) interface ................................................................................................ .................................... 20 interrupt (intrp) .............................................................................................................. ................................................ 20 mii data in terface ............................................................................................................. ................................................ 20 mii signal de finition.......................................................................................................... ................................................ 21 transmit cl ock (t xc) ........................................................................................................... ...................................... 21 transmit enab le (txen)......................................................................................................... .................................... 21 transmit data [3 :0] (txd[3:0])................................................................................................. .................................. 21 receive clo ck (rxc ) ............................................................................................................ ...................................... 21 receive data valid (rxdv) ...................................................................................................... .................................. 22 receive data [3 :0] (rxd[3:0]) .................................................................................................. .................................. 22 receive erro r (rxer)........................................................................................................... ...................................... 22 carrier sens e (crs) ............................................................................................................ ....................................... 22 collision (col) ................................................................................................................ ........................................... 22 reduced mii (rmii) data interface.............................................................................................. ..................................... 22 rmii signal de finition ......................................................................................................... .............................................. 23 reference clo ck (ref_c lk) ...................................................................................................... ............................... 23 transmit enab le (tx_en)........................................................................................................ ................................... 23 transmit data [1 :0] (txd[1:0])................................................................................................. .................................. 23 carrier sense/receive data valid (crs_dv) ...................................................................................... ..................... 23 receive data [1 :0] (rxd[1:0]) .................................................................................................. .................................. 23 receive erro r (rx_ er).......................................................................................................... ..................................... 23 collision de tection ............................................................................................................ ......................................... 24 serial mii (smii) data inte rface ............................................................................................... ......................................... 24 smii signal de finition ......................................................................................................... .............................................. 24 clock refere nce (clock) ........................................................................................................ ................................. 24 sync pul se (sy nc) .............................................................................................................. ....................................... 24 transmit data a nd control (tx) ................................................................................................. ............................... 24 receive data a nd control (rx).................................................................................................. ................................ 25 collision de tection ............................................................................................................ ......................................... 26 hp auto mdi/mdi -x.............................................................................................................. ............................................ 27 straight cable ................................................................................................................. ............................................ 27 crossover cable ................................................................................................................ ......................................... 28 linkmd ? cable diag nostics............................................................................................................. ................................. 29 access ......................................................................................................................... ................................................ 29 usage .......................................................................................................................... ................................................. 29
micrel, inc. KSZ8041TL/ftl april 2007 5 m9999-042707-1.1 power m anagem ent............................................................................................................... ........................................... 29 power savi ng mode.............................................................................................................. ...................................... 29 power down mode................................................................................................................ ...................................... 29 reference clock co nnection options ............................................................................................. ................................. 30 reference circuit for powe r and ground c onnections ............................................................................. ....................... 31 100base-fx fiber operat ion (ksz8041 ftl only) ................................................................................... ........................ 32 fiber signa l detect ............................................................................................................ ......................................... 32 far-end fault.................................................................................................................. ............................................. 32 back-to-back medi a converter................................................................................................... ...................................... 33 mii back-to-b ack mode .......................................................................................................... .................................... 33 rmii back-to-b ack mode......................................................................................................... ................................... 34 register map................................................................................................................... ..................................................... 35 register de scription ........................................................................................................... ................................................ 35 absolute maximum ratings (1) ............................................................................................................................... ............. 43 operating ratings (2) ............................................................................................................................... ............................. 43 electrical characteristics (3) ............................................................................................................................... ................. 43 timing di agrams ................................................................................................................ ................................................. 45 mii sqe timing (10bas e-t) ...................................................................................................... ....................................... 45 mii transmit timi ng (10base-t) ................................................................................................. ...................................... 46 mii receive timi ng (10base-t) .................................................................................................. ...................................... 47 mii transmit timi ng (100bas e-tx) ............................................................................................... ................................... 48 mii receive timi ng (100bas e-tx) ................................................................................................ ................................... 49 rmii timing.................................................................................................................... ................................................... 50 auto-negotiati on timi ng ........................................................................................................ ........................................... 51 mdc/mdio timing ................................................................................................................ ........................................... 52 reset timing................................................................................................................... .................................................. 53 reset ci rcuit .................................................................................................................. ...................................................... 54 selection of isolat ion transformer............................................................................................. ....................................... 56 selection of refe rence crystal ................................................................................................. ......................................... 56 package info rmation............................................................................................................ ............................................... 57
micrel, inc. KSZ8041TL/ftl april 2007 6 m9999-042707-1.1 list of figures figure 1. auto-negot iation flow chart......................................................................................... ........................................ 19 figure 2. smii transmit data/control segment.................................................................................. ................................. 25 figure 3. smii receiv e data/contro l segment................................................................................... ................................. 26 figure 4. typical stra ight cable connection ................................................................................... .................................... 27 figure 5. typical cros sover cable connection .................................................................................. ................................. 28 figure 6. 25mhz crystal / oscillat or reference cloc k for mii mode ............................................................. ...................... 30 figure 7. 50mhz oscillator re ference clock fo r rmii mode...................................................................... ......................... 30 figure 8. 125mhz oscillator reference clock for smii mode ..................................................................... ........................ 30 figure 9. KSZ8041TL/ftl po wer and ground connections.......................................................................... ..................... 31 figure 10. ksz8041ftl / KSZ8041TL ba ck-to-back medi a converter ................................................................ .............. 33 figure 11. mii sqe timing (10base-t) .......................................................................................... ..................................... 45 figure 12. mii transmi t timing (10base-t) ..................................................................................... .................................... 46 figure 13. mii receiv e timing (10base-t) ...................................................................................... .................................... 47 figure 14. mii transmi t timing (100base-tx)................................................................................... .................................. 48 figure 15. mii receiv e timing (100base-tx).................................................................................... .................................. 49 figure 16. rmii timing ? da ta received from rmii .............................................................................. .............................. 50 figure 17. rmii timing ? data input to rmii ................................................................................... .................................... 50 figure 18. auto-negotiation fa st link pulse (flp) ti ming ...................................................................... ........................... 51 figure 19. mdc/ mdio timing.................................................................................................... .......................................... 52 figure 20. re set timing....................................................................................................... ................................................ 53 figure 21. recommen ded reset circuit.......................................................................................... .................................... 54 figure 22. recommended reset circuit for interfacing with cpu/ fpga rese t output ............................................... ...... 54 figure 23. reference circui ts for led st rapping pins.......................................................................... ............................... 55
micrel, inc. KSZ8041TL/ftl april 2007 7 m9999-042707-1.1 list of tables table 1. mii mana gement frame format .......................................................................................... .................................. 20 table 2. mii si gnal definition ................................................................................................ ............................................... 21 table 3. rmii si gnal descri ption.............................................................................................. ............................................ 23 table 4. smii si gnal descri ption.............................................................................................. ............................................ 24 table 5. smii tx bit description .............................................................................................. ............................................ 25 table 6. smii txd[0: 7] encoding table ......................................................................................... ..................................... 25 table 7. smii rx bit description.............................................................................................. ............................................ 26 table 8. smii rxd[0: 7] encoding table ......................................................................................... ..................................... 26 table 9. mdi/mdi- x pin definition ............................................................................................. .......................................... 27 table 10. KSZ8041TL/ftl power pin de scription ................................................................................. ............................. 31 table 11. copper and fi ber mode se lection ..................................................................................... .................................. 32 table 12. mii signal connecti on for mii back -to-back mode ..................................................................... ......................... 33 table 13. rmii signal connecti on for rmii back-t o-back mode................................................................... ...................... 34 table 14. mii sqe timing (10base-t) parameters ................................................................................ ............................. 45 table 15. mii transmit ti ming (10base-t) parameters ........................................................................... ........................... 46 table 16. mii receive timi ng (10base-t) parameters ............................................................................ ........................... 47 table 17. mii transmit ti ming (100base-tx ) parameters ......................................................................... ......................... 48 table 18. mii receive timi ng (100base-tx) parameters .......................................................................... ......................... 49 table 19. rmii ti ming parameters .............................................................................................. ........................................ 50 table 20. auto-negotiation fast li nk pulse (flp) ti ming para meters ............................................................ ................... 51 table 21. mdc/mdio timing pa rameters .......................................................................................... ................................. 52 table 22. reset timing parameters ............................................................................................. ....................................... 53 table 23. transformer selection criteria ...................................................................................... ....................................... 56 table 24. qualified si ngle port m agnetics..................................................................................... ...................................... 56 table 25. typical referenc e crystal characteristics ........................................................................... ................................ 56
micrel, inc. KSZ8041TL/ftl april 2007 8 m9999-042707-1.1 pin configuration 1 nc nc txc rst# intrp rext gnd rxer / rx_er / iso gnd vdd_1.8 gnd gnd gnd gnd xo vdda_3.3 nc txd1 / txd[1] / sync txd0 / txd[0] / tx txen / tx_en led1 / speed led0 / nwayen crs / config1 nc 2 3 8 13 14 16 17 29 30 31 32 33 34 35 36 41 42 43 44 45 46 47 48 rx+ tx- rx- 9 10 11 gnd 24 txd3 txd2 gnd col / config0 37 38 39 40 rxc vddio_3.3 vddio_3.3 rxdv / crsdv / config2 25 26 27 28 rxd2 / phyad1 rxd1 / rxd[1] / phyad2 rxd0 / rxd[0] / rx duplex 21 22 23 mdio mdc rxd3 / phyad0 18 19 20 xi / refclk / clock 15 tx+ 12 vdda_1.8 vdda_1.8 4 5 v1.8_out vdda_3.3 6 7 KSZ8041TL 48-pin tqfp
micrel, inc. KSZ8041TL/ftl april 2007 9 m9999-042707-1.1 1 nc nc txc rst# intrp rext gnd rxer / rx_er / iso gnd vdd_1.8 gnd gnd gnd gnd xo vdda_3.3 fxsd / fxen txd1 / txd[1] / sync txd0 / txd[0] / tx txen / tx_en led1 / speed / no fef led0 / nwayen crs / config1 nc 2 3 8 13 14 16 17 29 30 31 32 33 34 35 36 41 42 43 44 45 46 47 48 rx+ tx- rx- 9 10 11 gnd 24 txd3 txd2 gnd col / config0 37 38 39 40 rxc vddio_3.3 vddio_3.3 rxdv / crsdv / config2 25 26 27 28 rxd2 / phyad1 rxd1 / rxd[1] / phyad2 rxd0 / rxd[0] / rx duplex 21 22 23 mdio mdc rxd3 / phyad0 18 19 20 xi / refclk / clock 15 tx+ 12 vdda_1.8 vdda_1.8 4 5 v1.8_out vdda_3.3 6 7 ksz8041ftl 48-pin tqfp
micrel, inc. KSZ8041TL/ftl april 2007 10 m9999-042707-1.1 pin description pin number pin name type (1) pin function 1 gnd gnd ground 2 gnd gnd ground 3 gnd gnd ground 4 vdda_1.8 p 1.8v analog v dd 5 vdda_1.8 p 1.8v analog v dd 6 v1.8_out p 1.8v output voltage from chip 7 vdda_3.3 p 3.3v analog v dd 8 vdda_3.3 p 3.3v analog v dd 9 rx- i/o physical receive or transmit signal (- differential) 10 rx+ i/o physical receive or transmit signal (+ differential) 11 tx- i/o physical transmit or receive signal (- differential) 12 tx+ i/o physical transmit or receive signal (+ differential) 13 gnd gnd ground 14 xo o crystal feedback this pin is used only in mii mode when a 25 mhz crystal is used. this pin is a no connect if oscillator or external clock source is used, or if rmii mode or smii mode is selected. 15 xi / refclk / clock i crystal / oscillator / external clock input mii mode: 25mhz +/-50ppm (crystal, oscillator, or external clock) rmii mode: 50mhz +/-50ppm (oscillator, or external clock only) smii mode: 125mhz +/-100ppm (oscillator, or external clock only) 16 rext i/o set physical transmit output current connect a 6.49k ? resistor in parallel with a 100pf capacitor to ground on this pin. see KSZ8041TL-ftl reference schematics. 17 gnd gnd ground 18 mdio i/o management interface (mii) data i/o this pin requires an external 4.7k ? pull-up resistor. 19 mdc i management interface (mii) clock input this pin is synchronous to the mdio data interface. 20 rxd3 / phyad0 ipu/o mii mode: receive data output[3] (2) / config mode: the pull-up/pull-down va lue is latched as phyaddr[0] during power-up / reset. see ?strapping options? section for details. 21 rxd2 / phyad1 ipd/o mii mode: receive data output[2] (2) / config mode: the pull-up/pull-down va lue is latched as phyaddr[1] during power-up / reset. see ?strapping options? section for details. 22 rxd1 / rxd[1] / phyad2 ipd/o mii mode: receive data output[1] (2) / rmii mode: receive data output[1] (3) / config mode: the pull-up/pull-down va lue is latched as phyaddr[2] during power-up / reset. see ?strapping options? section for details.
micrel, inc. KSZ8041TL/ftl april 2007 11 m9999-042707-1.1 pin number pin name type (1) pin function 23 rxd0 / rxd[0] / rx duplex ipu/o mii mode: receive data output[0] (2) / rmii mode: receive data output[0] (3) / smii mode: receive data and control (4) / config mode: latched as duplex (r egister 0h, bit 8) during power-up / reset. see ?strapping options? section for details. 24 gnd gnd ground 25 vddio_3.3 p 3.3v digital v dd 26 vddio_3.3 p 3.3v digital v dd 27 rxdv / crsdv / config2 ipd/o mii mode: receive data valid output / rmii mode: carrier sense/receive data valid output / config mode: the pull-up/pull-down value is latched as config2 during power-up / reset. see ?strapping options? section for details. 28 rxc o mii mode: receive clock output 29 rxer / rx_er / iso ipd/o mii mode: receive error output / rmii mode: receive error output / config mode: the pull-up/pull-down value is latched as isolate during power-up / reset. see ?strapping options? section for details. 30 gnd gnd ground 31 vdd_1.8 p 1.8v digital v dd 32 intrp opu interrupt output: programmable interrupt output register 1bh is the interrupt contro l/status register for programming the interrupt conditions and reading the interrupt status. register 1fh bit 9 sets the interrupt output to active low (default) or active high. 33 txc i/o mii mode: transmit clock output mii back-to back mode: transmit clock input 34 txen / tx_en i mii mode: transmit enable input / rmii mode: transmit enable input 35 txd0 / txd[0] / tx i mii mode: transmit data input[0] (5) / rmii mode: transmit data input[0] (6) / smii mode: transmit data and control (7) 36 txd1 / txd[1] / sync i mii mode: transmit data input[1] (5) / rmii mode: transmit data input[1] (6) / smii mode: sync clock input 37 gnd gnd ground 38 txd2 i mii mode: transmit data input[2] (5) / 39 txd3 i mii mode: transmit data input[3] (5) / 40 col / config0 ipd/o mii mode: collision detect output / config mode: the pull-up/pull-down value is latched as config0 during power-up / reset. see ?strapping options? section for details. 41 crs / config1 ipd/o mii mode: carrier sense output / config mode: the pull-up/pull-down value is latched as config1 during power-up / reset. see ?strapping options? section for details.
micrel, inc. KSZ8041TL/ftl april 2007 12 m9999-042707-1.1 pin number pin name type (1) pin function 42 (KSZ8041TL) led0 / nwayen ipu/o led output: programmable led0 output / config mode: latched as auto-negotiation enable (register 0h, bit 12) during power-up / reset. see ?strapping options? section for details. the led0 pin is programmable via regist er 1eh bits [15:14], and is defined as follows. led mode = [00] link/activity pin state led definition no link h off link l on activity toggle blinking led mode = [01] link pin state led definition no link h off link l on led mode = [10] reserved led mode = [11] reserved 42 (ksz8041ftl) led0 / nwayen ipu/o led output: programmable led0 output / config mode: if copper mode (fxen=0), latched as auto-negotiation enable (register 0h, bit 12) during power-up / reset. if fiber mode (fxen=1), this pin configuration is always strapped to disable auto-negotiation. see ?strapping options? section for details. the led0 pin is programmable via regist er 1eh bits [15:14], and is defined as follows. led mode = [00] link/activity pin state led definition no link h off link l on activity toggle blinking led mode = [01] link pin state led definition no link h off link l on led mode = [10] reserved led mode = [11] reserved
micrel, inc. KSZ8041TL/ftl april 2007 13 m9999-042707-1.1 pin number pin name type (1) pin function 43 (KSZ8041TL) led1 / speed ipu/o led output: programmable led1 output / config mode: latched as speed (register 0h, bit 13) during power-up / reset. see ?strapping options? section for details. the led1 pin is programmable via regist er 1eh bits [15:14], and is defined as follows. led mode = [00] speed pin state led definition 10bt h off 100bt l on led mode = [01] activity pin state led definition no activity h off activity toggle blinking led mode = [10] reserved led mode = [11] reserved 43 (ksz8041ftl) led1 / speed / no fef ipu/o led output: programmable led1 output / config mode: if copper mode (fxen=0) , latched as speed (register 0h, bit 13) during power-up / reset. if fiber mode (fxen=1), latched as no fef (no far-end fault) during power-up / reset. see ?strapping options? section for details. the led1 pin is programmable via regist er 1eh bits [15:14], and is defined as follows. led mode = [00] speed pin state led definition 10bt h off 100bt l on led mode = [01] activity pin state led definition no activity h off activity toggle blinking led mode = [10] reserved led mode = [11] reserved 44 nc - no connect 45 nc - no connect 46 nc - no connect
micrel, inc. KSZ8041TL/ftl april 2007 14 m9999-042707-1.1 pin number pin name type (1) pin function 47 rst# i chip reset (active low) 48 (KSZ8041TL) nc - no connect 48 (ksz8041ftl) fxsd / fxen ipd fxsd: signal detect for 100base-fx fiber mode fxen: fiber enable for 100base-fx fiber mode if fxen=0, fiber mode is disabled. phy is in copper mode. the default is ?0?. see ?100base-fx operation? section for details. notes: 1. p = power supply. gnd = ground. i = input. o = output. i/o = bi-directional. ipd = input with internal pull-down (40k +/-30%). ipu = input with internal pull-up (40k +/-30%). opu = output with internal pull-up (40k +/-30%). ipu/o = input with internal pull-up (40k +/-30%) during power-up/reset; output pin otherwise. ipd/o = input with internal pull-down (40k +/-30%) during power-up/reset; output pin otherwise. 2. mii rx mode: the rxd[3..0] bits are synchronous with rxclk. when rxdv is asserted, rxd[3..0] presents valid data to mac th rough the mii. rxd[3..0] is invalid when rxdv is de-asserted. 3. rmii rx mode: the rxd[1:0] bits are synchronous with ref_cl k. for each clock period in which crs_dv is asserted, two bits of recovered data are sent from the phy. 4. smii rx mode: receive data and control information are sent in 10 bit segments. in 100mbit mode, each segment represents a new byte of data. in 10mbit mode, each segment is repeated ten times; theref ore, every ten segments represent a new byte of data. the mac can sample any one of every 10 segments in 10mbit mode. 5. mii tx mode: the txd[3..0] bits are synchronous with txclk. when txen is asserted, txd[3..0] presents valid data from the mac through the mii. txd[3..0] has no effect when txen is de-asserted. 6. rmii tx mode: the txd[1:0] bits are synchronous with ref_cl k. for each clock period in which tx_en is asserted, two bits o f data are received by the phy from the mac. 7. smii tx mode: transmit data and control information are rece ived in 10 bit segments. in 100m bit mode, each segment represe nts a new byte of data. in 10mbit mode, each segment is repeated ten times; t herefore, every ten segments represent a new byte of data. the phy can sample any one of every 10 segments in 10mbit mode.
micrel, inc. KSZ8041TL/ftl april 2007 15 m9999-042707-1.1 strapping options pin number pin name type (1) pin function 22 21 20 phyad2 phyad1 phyad0 ipd/o ipd/o ipu/o the phy address is latched at power-up / reset and is configurable to any value from 1 to 7. the default phy address is 00001. phy address bits [4:3] ar e always set to ?00?. 27 41 40 config2 config1 config0 ipd/o ipd/o ipd/o the config[2:0] strap-in pins are latched at power-up / reset and are defined as follows: config[2:0] mode 000 mii (default) 001 rmii 010 smii 011 reserved ? not used 100 pcs loopback 101 rmii back-to-back 110 mii back-to-back 111 reserved ? not used 29 iso ipd/o isolate mode pull-up = enable pull-down (default) = disable during power-up / reset, this pin value is latched into register 0h bit 10. 43 (KSZ8041TL) speed ipu/o speed mode pull-up (default) = 100mbps pull-down = 10mbps during power-up / reset, this pin value is latched into register 0h bit 13 as the speed select, and also is latched into register 4h (auto-negotiation advertisement) as the speed capability support. 43 (ksz8041ftl) speed / no fef ipu/o if copper mode (fxen=0), pin strap-in is speed mode. pull-up (default) = 100mbps pull-down = 10mbps during power-up / reset, this pin value is latched into register 0h bit 13 as the speed select, and also is latched into register 4h (auto-negotiation advertisement) as the speed capability support. if fiber mode (fxen=1), pin strap-in is no fef. pull-up (default) = enable far-end fault pull-down = disable far-end fault this pin value is latched during power-up / reset.
micrel, inc. KSZ8041TL/ftl april 2007 16 m9999-042707-1.1 pin number pin name type (1) pin function 23 duplex ipu/o duplex mode pull-up (default) = half duplex pull-down = full duplex during power-up / reset, this pin value is latched into register 0h bit 8 as the duplex mode. 42 (KSZ8041TL) nwayen ipu/o nway auto -negotiation enable pull-up (default) = enable auto-negotiation pull-down = disable auto-negotiation during power-up / reset, this pin value is latched into register 0h bit 12. 42 (ksz8041ftl) nwayen ipu/o if copper mode (fxen=0), pin st rap-in is nway auto-negotiation enable. pull-up (default) = enable auto-negotiation pull-down = disable auto-negotiation during power-up / reset, this pin value is latched into register 0h bit 12. if fiber mode (fxen=1), this pin configuration is always strapped to disable auto- negotiation. note: 1. ipu/o = input with internal pull-up (40k +/-30%) during power-up/reset; output pin otherwise. ipd/o = input with internal pull-down (40k +/-30%) during power-up/reset; output pin otherwise. pin strap-ins are latched during power-up or reset. in some systems, the mac receive input pins may drive high during power-up or reset, and consequently cause the phy strap-in pins on the mii/rm ii/smii signals to be latched high. in this case, it is recommended to add 1k pull-downs on these phy strap-in pins to ensure the phy does not strap-in to isolate or pcs loopback mode, or is not configured with an incorrect phy address.
micrel, inc. KSZ8041TL/ftl april 2007 17 m9999-042707-1.1 functional description the KSZ8041TL is a single 3.3v supply fast ethernet transceiver. it is fully compli ant with the ieee 802.3u specification. on the media side, the KSZ8041TL supports 10base-t and 100b ase-tx with hp auto mdi/mdi-x for reliable detection of and correction for straight-through and crossover cables. the KSZ8041TL offers a choice of mii, rmii, or smii data inte rface connection to a mac processor. the mii management bus option gives the mac processor complete access to the KSZ8041TL control and status registers. additionally, an interrupt pin eliminates the need for the pr ocessor to poll for phy status change. physical signal transmission and reception are enhanced th rough the use of patented analog circuitries that make the design more efficient and allow for lower power consumption and smaller chip die size. the ksz8041ftl has all the identical rich features of the KSZ8041TL plus 100base-fx fiber support. 100base-tx transmit the 100base-tx transmit function performs parallel-to-s erial conversion, 4b/5b codi ng, scrambling, nrz-to-nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel-to-serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5 b coding, followed by a scrambler. the serialized data is further converted from nrz-to-nrzi format, and then transmitted in mlt3 current output. the output current is set by an external 6.49 k ? 1% resistor for the 1:1 transformer ratio. it has typical rise/fall times of 4 ns and complies with the ansi tp-pmd standard regarding amplitude balance, ov ershoot and timing jitter. the wave- shaped 10base-t output drivers are also incorporated into the 100base-tx drivers. 100base-tx receive the 100base-tx receiver function perfo rms adaptive equalization, dc restoration, mlt3-to-nr zi conversion, data and clock recovery, nrzi-to-nrz conversion, de-scrambling, 4b/5b decoding, and serial-to-parallel conversion. the receiving side starts with the equalizati on filter to compensate for inter-symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. in this design, the variable equalizer makes an initial estimation based upon comparisons of incoming signal strength against some known cabl e characteristics, and then tunes itself for optimization. this is an ongoing process and self-adjusts against envir onmental changes such as temperature variations. next, the equalized signal goes through a dc restoration and dat a conversion block. the dc restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 1 25mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this si gnal is sent through the de-sc rambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the mii format and provided as the input data to the mac. pll clock synthesizer the KSZ8041TL/ftl generates 125 m z, 25 m z and 20 m z clocks for system timing. internal clocks are generated from an external 25 mhz crystal or osc illator. in rmii mode, these internal cl ocks are generated from an external 50 mhz oscillator or system clock. scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spr ead the power spectrum of the signal in order to reduce emi and baseline wander. 10base-t transmit the 10base-t drivers are incorporated wi th the 100base-tx drivers to allow for transmission using the same magnetic. the drivers also perform internal wave -shaping and pre-emphasize, and output 10b ase-t signals with a typical amplitude of 2.5v peak. the 10base-t signals ha ve harmonic contents that are at leas t 27db below the fundamental frequency when driven by an all-ones manchester-encoded signal.
micrel, inc. KSZ8041TL/ftl april 2007 18 m9999-042707-1.1 10base-t receive on the receive side, input buffer and level detecting squelch ci rcuits are employed. a differential input receiver circuit and a pll performs the decoding function. the manchester-encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400 mv or with short pulse widths to prevent noise at the rx+ and rx- inputs from falsely trigger the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the KSZ8041TL/ftl decodes a data frame. the rece ive clock is kept active during idle periods in between data reception. sqe and jabber function (10base-t only) in 10base-t operation, a short pulse is put out on the col pin after each frame is transmitted. this sqe test is required as a test of the 10base-t transmit/recei ve path. if transmit enable (txen) is high for more than 20 ms (jabbering), the 10base-t transmitter is disabled and col is asserted high. if txen is then driven low for more than 250 ms, the 10base- t transmitter is re-enabled and col is de-asserted (returns to low). auto-negotiation the KSZ8041TL/ftl conforms to the auto- negotiation protocol, defined in clause 28 of the ieee 802.3u specification. auto-negotiation is enabled by either hardware pin st rapping (pin 30) or software (register 0h bit 12). auto-negotiation allows unshielded twisted pair (utp) link partn ers to select the highest common mode of operation. link partners advertise their capabilities to each other, and then co mpare their own capabilities with those they received from their link partners. the highest speed and du plex setting that is common to the two link partners is selected as the mode of operation. the following list shows the speed and duplex operation mode from highest to lowest. ? priority 1: 100base-tx, full-duplex ? priority 2: 100base-tx, half-duplex ? priority 3: 10base-t, full-duplex ? priority 4: 10base-t, half-duplex if auto-negotiation is not supported or the KSZ8041TL/ftl link partner is forced to bypass auto-negotiation, the KSZ8041TL/ftl sets its operating mode by observing the signal at its receiver. this is known as parallel detection, and allows the KSZ8041TL/ftl to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. the auto-negotiation link up process is shown in the following flow chart.
micrel, inc. KSZ8041TL/ftl april 2007 19 m9999-042707-1.1 start auto negotiation force link setting listen for 10base-t link pulses listen for 100base-tx idles a ttempt auto negotiation link mode set bypass auto negotiation and set link mode link mode set ? parallel operation join flow n o yes yes no figure 1. auto-negotiation flow chart
micrel, inc. KSZ8041TL/ftl april 2007 20 m9999-042707-1.1 mii management (miim) interface the KSZ8041TL/ftl supports the ieee 802.3 mii management in terface, also known as t he management data input / output (mdio) interface. this interface allows upper-l ayer devices to monitor and control the state of the KSZ8041TL/ftl. an external device with miim capability is used to read the phy status and/or configure the phy settings. further detail on the miim interface can be f ound in clause 22.2.4.5 of t he ieee 802.3u specification. the miim interface consists of the following: ? a physical connection that incorporates t he clock line (mdc) and the data line (mdio). ? a specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with one or more KSZ8041TL/ftl devices. each KSZ8041TL/ftl device is assigned a phy address between 1 and 7 by the phyad[2:0] strapping pins. ? an internal addressable set of thirteen 16-bit mdio regi sters. register [0:6] are r equired, and their functions are defined by the ieee 802.3u specificatio n. the additional registers are pr ovided for expanded functionality. the KSZ8041TL/ftl supports miim in mii mode, rmii mode and smii mode. the following table shows the mii management frame format for the KSZ8041TL/ftl. preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1?s 01 10 00aaa rrrrr z0 dddddddd_dddddddd z write 32 1?s 01 01 00aaa rrrrr 10 dddddddd_dddddddd z table 1. mii management frame format interrupt (intrp) intrp (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status update in the KSZ8041TL/ftl phy register. bits[15:8] of regist er 1bh are the interrupt control bits, and are used to enable and disable the conditions for asserting the intrp signal. bi ts[7:0] of register 1bh are the interrupt status bits, and are used to indicate which interrupt conditions have occurred . the interrupt status bits ar e cleared after reading register 1bh. bit 9 of register 1fh sets the interrupt level to active high or active low. mii data interface the media independent in terface (mii) is specified in clause 22 of the ieee 802.3u specification. it provides a common interface between physical layer and mac layer devic es, and has the following key characteristics: ? supports 10mbps and 100mbps data rates. ? uses a 25 mhz reference cl ock, sourced by the phy. ? provides independent 4-bit wide (nibble) transmit and receive data paths. ? contains two distinct groups of signals: one for transmission and the other for reception. by default, the KSZ8041TL/ftl is configured in mii mode a fter it is power-up or reset with the following: ? a 25 mhz crystal connected to xi, xo (pins 15, 14), or an external 25mhz cl ock source (oscillato r) connected to xi. ? config[2:0] (pins 27, 41, 40) set to ?000? (default setting).
micrel, inc. KSZ8041TL/ftl april 2007 21 m9999-042707-1.1 mii signal definition the following table describes the mii sig nals. refer to clause 22 of the ieee 802. 3u specification for det ailed information. mii signal name direction (with respect to phy, KSZ8041TL/ftl signal) direction (with respect to mac) description txc output input transmit clock (2.5 mhz for 10mbps; 25 mhz for 100mbps) txen input output transmit enable txd[3:0] input output transmit data [3:0] rxc output input receive clock (2.5 mhz for 10mbps; 25 mhz for 100mbps) rxdv output input receive data valid rxd[3:0] output input receive data [3:0] rxer output input, or (not required) receive error crs output input carrier sense col output input collision detection table 2. mii signal definition transmit clock (txc) txc is sourced by the phy. it is a continuous clock t hat provides the timing reference for txen and txd[3:0]. txc is 2.5mhz for 10mbps operation and 25mhz for 100mbps operation. transmit enable (txen) txen indicates the mac is presenting nibbles on txd[3:0] for transmission. it is asserted synchronously with the first nibble of the preamble and re mains asserted while all nibbles to be tran smitted are presented on the mii, and is negated prior to the first txc following the final nibble of a frame. txen transitions synchronous ly with respect to txc. transmit data [3:0] (txd[3:0]) txd[3:0] transitions synchronously with respect to txc. when txen is asserted, txd[3:0] are accepted for transmission by the phy. txd[3:0] is ?00? to indica te idle when txen is de-asserted. values other than ?00? on txd[3:0] while txen is de-asserted are ignored by the phy. receive clock (rxc) rxc provides the timing reference for rxdv, rxd[3:0], and rxer. ? in 10mbps mode, rxc is recovered from the line while carr ier is active. rxc is derived from the phy?s reference clock when the line is idle, or link is down. ? in 100mbps mode, rxc is continuously recovered from t he line. if link is down, rxc is derived from the phy?s reference clock. rxc is 2.5mhz for 10mbps operation and 25mhz for 100mbps operation.
micrel, inc. KSZ8041TL/ftl april 2007 22 m9999-042707-1.1 receive data valid (rxdv) rxdv is driven by the phy to indicate that the phy is presenting recovered and decoded nibbles on rxd[3:0]. ? in 10mbps mode, rxdv is asserted with the first nibble of the sfd (start of frame delimiter), ?5d?, and remains asserted until the end of the frame. ? in 100mbps mode, rxdv is asserted from the first nibbl e of the preamble to the last nibble of the frame. rxdv transitions synchronously with respect to rxc. receive data [3:0] (rxd[3:0]) rxd[3:0] transitions synchronously with respect to rxc. for each clock period in which rxdv is asserted, rxd[3:0] transfers a nibble of recovered data from the phy. receive error (rxer) rxer is asserted for one or more rxc periods to indicate that a symbol error (e.g. a coding error that a phy is capable of detecting, and that may otherwise be undetectable by t he mac sub-layer) was detected somewhere in the frame presently being transferred from the phy. rxer transitions synchronously with re spect to rxc. while rxdv is de-assert ed, rxer has no effect on the mac. carrier sense (crs) crs is asserted and de-asserted as follows: ? in 10mbps mode, crs assertion is based on the recept ion of valid preambles. crs de-assertion is based on the reception of an end-of-frame (eof) marker. ? in 100mbps mode, crs is asserted when a start-of-stream delimiter, or /j/k symbol pair is detected. crs is de- asserted when an end-of-stream delimiter, or /t/r symbol pair is detected. additionally, the pma layer de-asserts crs if idle symbols are received without /t/r. collision (col) col is asserted in half-duplex mode whenever the transmitter an d receiver are simultaneously active on the line. this is used to inform the mac that a collision has oc curred during its transmission to the phy. col transitions asynchronously with respect to txc and rxc. reduced mii (rmii) data interface the reduced media independent interface (rmii) specifies a low pin count media independent interface (mii). it provides a common interface between physical layer and mac layer devices, and has the following key characteristics: ? supports 10mbps and 100mbps data rates. ? uses a single 50 mhz reference clock pr ovided by the mac or the system board. ? provides independent 2-bit wide (di-bit) transmit and receive data paths. ? contains two distinct groups of signals: one for transmission and the other for reception. the KSZ8041TL/ftl is configured in rmii mode after it is power-up or reset with the following: ? a 50 mhz reference clock connected to refclk (pin 15). ? config[2:0] (pins 27, 41, 40) set to ?001?. in rmii mode, unused mii signals, txd[3:2] (pins 39, 38), are tied to ground.
micrel, inc. KSZ8041TL/ftl april 2007 23 m9999-042707-1.1 rmii signal definition the following table describes the rmii signals. refe r to rmii specification for detailed information. rmii signal name direction (with respect to phy, KSZ8041TL/ftl signal) direction (with respect to mac) description ref_clk input input, or output synchronous 50 mhz clock reference for receive, transmit and control interface tx_en input output transmit enable txd[1:0] input output transmit data [1:0] crs_dv output input carrier sense/receive data valid rxd[1:0] output input receive data [1:0] rx_er output input, or (not required) receive error table 3. rmii signal description reference clock (ref_clk) ref_clk is sourced by the mac or system board. it is a cont inuous 50 mhz clock that provi des the timing reference for tx_en, txd[1:0], crs_dv, rxd[1:0], and rx_er. transmit enable (tx_en) tx_en indicates that the mac is presenting di-bits on txd[1:0] for transmission. it is asserted synchronously with the first nibble of the preamble and remains asserted while all di-bit s to be transmitted are pres ented on the rmii, and is negated prior to the first ref_clk following the final di-bit of a frame. tx_en transitions synchronously with respect to ref_clk. transmit data [1:0] (txd[1:0]) txd[1:0] transitions synchronously with respect to ref_clk. when tx_en is asserted, txd[1:0] are accepted for transmission by the phy. txd[1:0] is ?00? to indicate idle when tx_en is de- asserted. values other t han ?00? on txd[1:0] while tx_en is de-asserted are ignored by the phy. carrier sense/receive data valid (crs_dv) crs_dv is asserted by the phy when t he receive medium is non-idle. it is asserted asynchronously on detection of carrier. this is when squelch is passed in 10mbps mode, and when 2 non-contiguous zeroes in 10 bits are detected in 100mbps mode. loss of carrier result s in the de-assertion of crs_dv. so long as carrier detection criteria are met, crs_dv remains as serted continuously from the first recovered di-bit of the frame through the final recovered di-bit, and it is negated prior to the first ref_clk that follows the final di-bit. the data on rxd[1:0] is considered valid once crs_dv is asserted. however, since the assertion of crs_dv is asynchronous relative to ref_clk, the data on rxd[1:0] is " 00" until proper receive signal decoding takes place. receive data [1:0] (rxd[1:0]) rxd[1:0] transitions synchronously to ref_ clk. for each clock period in which cr s_dv is asserted, rxd[1:0] transfers two bits of recovered data from the phy. rxd[1:0] is "00" to indicate idle when crs_dv is de-asserted. values other than ?00? on rxd[1:0] while crs_dv is de-asserted are ignored by the mac. receive error (rx_er) rx_er is asserted for one or more ref_clk periods to indica te that a symbol error (e.g. a coding error that a phy is capable of detecting, and that may otherwise be undetect able by the mac sub-layer) wa s detected somewhere in the frame presently being transferred from the phy. rx_er transitions synchronously with respect to ref_clk. while crs_dv is de-asserted, rx_er has no effect on the mac.
micrel, inc. KSZ8041TL/ftl april 2007 24 m9999-042707-1.1 collision detection the mac regenerates the col signal of the mii from tx_en and crs_dv. serial mii (smii) data interface the serial media independent interface (smii) is the lowest pin count media independent interface (mii). it provides a common interface between physical layer and mac layer dev ices, and has the following key characteristics: ? supports 10mbps and 100mbps data rates. ? uses 125 mhz reference clock provid ed by the mac or the system board. ? uses 12.5 mhz sync puls e provided by the mac. ? provides independent single-bit wide transmit and re ceive data paths for data and control information. the KSZ8041TL/ftl is configured in smii mode after it is power-up or reset with the following: ? a 125 mhz reference clock connected to clock (pin 15). ? a 12.5 mhz sync pulse connected to sync (pin 36). ? config[2:0] (pins 27, 41, 40) set to ?010?. in smii mode, unused mii signals, txd[3:2] (pins 39, 38), are tied to ground. smii signal definition the following table describes the smii signals. refe r to smii specification for detailed information. smii signal name direction (with respect to phy, KSZ8041TL/ftl signal) direction (with respect to mac) description clock input input, or output 125 mhz clock reference for receive and transmit data and control sync input output 12.5 mhz sync pulse from mac tx input output transmit data and control rx output input receive data and control table 4. smii signal description clock reference (clock) clock is sourced by the mac or system board. it is a contin uous 125 mhz clock that provides the timing reference for sync, tx, and rx. sync pulse (sync) sync is a 12.5 mhz synchronized pulse de rived from clock by the mac. it is used to indicate the segment boundary for each transmit data/control segment, or receive data/cont rol segment. each segment is comprised of ten bits. sync is generated continuously by the mac at every ten cycles of clock. transmit data and control (tx) tx provides transmit data and control inform ation from mac-to-phy in 10-bit segments. ? in 10mbps mode, each segment is rep eated ten times. therefore, every t en segments represent a new byte of data. the phy can sample any one of every ten segments. ? in 100mbps mode, each segment represents a new byte of data.
micrel, inc. KSZ8041TL/ftl april 2007 25 m9999-042707-1.1 the following figure and table shows the transmit data/control format for each segment: tx_er tx_en txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 clock sync tx figure 2. smii transmit data/control segment smii tx bit description tx_er transmit error tx_en transmit enable txd[0:7] encoded data see smii txd[0:7] encoding table (below) table 5. smii tx bit description tx_er tx_en txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 x 0 use to force an error in a direct mac-to- mac connection speed 0=10m 1=100m duplex 0=half 1=full link 0=down 1=up jabber 0=no 1=yes 1 1 1 x 1 one data byte table 6. smii txd[0:7] encoding table receive data and control (rx) rx provides receive data and control inform ation from phy-to-mac in 10-bit segments. ? in 10mbps mode, each segment is rep eated ten times. therefore, every t en segments represent a new byte of data. the mac can sample any one of every ten segments. ? in 100mbps mode, each segment represents a new byte of data.
micrel, inc. KSZ8041TL/ftl april 2007 26 m9999-042707-1.1 the following figure and table shows the receive data/control format for each segment: crs rx_dv rxd0 rxd1 rxd2 r xd3 rxd4 rxd5 rxd6 rxd7 clock sync rx figure 3. smii receive data/control segment smii rx bit description crs carrier sense rx_dv receive data valid rxd[0:7] encoded data see smii rxd[0:7] encoding table (below) table 7. smii rx bit description crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 x 0 rx_er from pervious frame speed 0=10m 1=100m duplex 0=half 1=full link 0=down 1=up jabber 0=no 1=yes upper nibble 0=invalid 1=valid false carrier detected 1 x 1 one data byte table 8. smii rxd[0:7] encoding table collision detection collisions occur when crs and tx_en are si multaneously asserted. the mac regener ates the mii collision signal from crs and tx_en.
micrel, inc. KSZ8041TL/ftl april 2007 27 m9999-042707-1.1 hp auto mdi/mdi-x hp auto mdi/mdi-x configuration elimi nates the confusion of whether to use a straight cable or a crossover cable between the KSZ8041TL/ftl and its link part ner. this feature allows the KSZ8041TL/ftl to use either type of cable to connect with a link partner that is in either mdi or mdi- x mode. the auto-sense function detects transmit and receive pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8041TL/ftl accordingly. hp auto mdi/mdi-x is enabled by default. it is disabled by wr iting a one to register 1f bit 13. mdi and mdi-x mode is selected by register 1f bit 14 if hp auto mdi/mdi-x is disabled. an isolation transformer with symmetrical transmit and re ceive data paths is recommended to support auto mdi/mdi-x. the ieee 802.3u standard defines mdi and mdi-x as follow: mdi mdi-x rj-45 pin signal rj-45 pin signal 1 td+ 1 rd+ 2 td- 2 rd- 3 rd+ 3 td+ 6 rd- 6 td- table 9. mdi/mdi-x pin definition straight cable a straight cable connects a mdi device to a mdi-x device, or a mdi-x device to a mdi device. the following diagram depicts a typical straight cable connection between a nic card (mdi ) and a switch, or hub (mdi-x). receive pair transmit pair receive pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair modular connector (rj-45) nic straight cable 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch) figure 4. typical straight cable connection
micrel, inc. KSZ8041TL/ftl april 2007 28 m9999-042707-1.1 crossover cable a crossover cable connects a mdi device to another mdi device, or a mdi-x device to another mdi-x device. the following diagram depicts a typical crossover cable connect ion between two switches or hubs (two mdi-x devices). receive pair receive pair transmit pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch) modular connector (rj-45) hub (repeater or switch) crossover cable figure 5. typical crossover cable connection
micrel, inc. KSZ8041TL/ftl april 2007 29 m9999-042707-1.1 linkmd ? cable diagnostics the linkmd ? feature utilizes time domain reflectometry (tdr) to analyze the cabling plant for common cabling problems, such as open circuits, short circuits and impedance mismatches. linkmd ? works by sending a pulse of known amplitude and du ration down the mdi and mdi-x pairs, and then analyzing the shape of the reflected signal. timing the pulse duration gi ves an indication of the distance to the cabling fault with maximum distance of 200m and accuracy of +/-2m. internal ci rcuitry computes the tdr information and presents it in a user-readable digital format. note: cable diagnostics are only valid for copper connections and do not support fiber optic operation. access linkmd ? is initiated by accessing register 1dh, the linkmd ? control/status register, in conj unction with register 1fh, the phy control 2 register. usage the following test procedure demonstrates how to use linkmd ? for cable diagnostic: 1. disable auto mdi/mdi-x by writing a ?1? to register 1fh bit 13 to enable manual control over the differential pair used to transmit the linkmd ? pulse. 2. select the differential pair to transmit the linkmd ? pulse with register 1fh bit 14. 3. start cable diagnostic test by writing a ?1? to r egister 1dh bit 15. this enable bit is self-clearing. 4. wait (poll) for register 1dh bit 15 to return a ?0?, indicating cable diagnostic test is completed. 5. read cable diagnostic test results in regist er 1dh bits [14:13]. the results are as follows: 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) 11 = cable diagnostic test failed (invalid test) the ?11? case, invalid test, occurs if the KSZ8041TL/ftl is unable to shut down the link partner. in this instance, the test is not run, since it would be impossible for the KSZ8041TL/ftl to determine if the detected signal is a reflection of the signal generated by the ksz 8041tl/ftl, or a signal from its link partner. 6. get distance to fault by multiplying the decimal value in register 1dh bits [8:0] by a co nstant of 0.4. the distance, d (expressed in meters), to the cable faul t is determined by the following formula: d (distance to cable fault) = 0.4 x {decimal value of register 1dh bits [8:0]} the 0.4 constant can be calibrated for different cable types and cabling conditions, such as cables with velocity of propagation that varies significantly from the norm. power management the KSZ8041TL/ftl offers the following power management modes: power saving mode this mode is used to reduce power consumption when the cable is unplugged. it is in effect when auto-negotiation mode is enabled, cable is disconnected, and register 1fh bit 10 is set to 1 (default setting). under power saving mode, the KSZ8041TL/ftl shuts down all transceiver blocks, except for energy detect and pll circuits. additionally, in mii mode, the rxc clock output is dis abled. rxc clock is enabled after the cabl e is connected and link is established. power saving mode is disabled by writing a zero to register 1fh bit 10. power down mode this mode is used to power down the entire KSZ8041TL/ftl device when it is not in use. power down mode is enabled by writing a one to register 0h bit 11. in the power down st ate, the KSZ8041TL/ftl disables all internal functions, except for the mii management interface.
micrel, inc. KSZ8041TL/ftl april 2007 30 m9999-042707-1.1 reference clock connection options a crystal or clock source, su ch as an oscillator, is used to provide the reference clock fo r the KSZ8041TL/ftl. the reference clock is 25 mhz for mii mode, 50 mhz for rmii mode, and 125 mhz for smii mode. the following three figures illustrate how to connect the reference clock to xi / refc lk / clock (pin 9) and xo (pin 8) of the KSZ8041TL/ftl. 25mhz osc +/-50ppm nc nc xi xo xi xo 22pf 22pf 22pf 22pf 25mhz xtal +/-50ppm figure 6. 25mhz crystal / oscilla tor reference clock for mii mode figure 7. 50mhz oscillator re ference clock for rmii mode 125mhz osc +/-100ppm nc nc clock xo figure 8. 125mhz oscillator re ference clock for smii mode
micrel, inc. KSZ8041TL/ftl april 2007 31 m9999-042707-1.1 reference circuit for power and ground connections the KSZ8041TL/ftl is a single 3.3v supply device with a built-in 1.8v low noise regulator. the power and ground connections are shown in the following figure and table. figure 9. KSZ8041TL/ftl power and ground connections power pin pin number pin type description v1.8_out 6 output 1.8v supp ly output from KSZ8041TL/ftl decouple with 22uf and 0.1uf capacitors-to-ground. vdd_1.8 31 input connect to v1.8_out (pin 6) thru ferrite bead. decouple with 0.1uf capacitor-to-ground. vdda_1.8 4, 5 input connect to v1. 8_out (pin 6) thru ferrite bead. decouple with 0.1uf capacitor on each pin-to-ground. vddio_3.3 25, 26 input connec t to board?s 3.3v supply. decouple with 22uf and 0.1uf capacitors-to-ground. vdda_3.3 7, 8 input connect to board?s 3.3v supply thru ferrite bead. decouple with 22uf and 0.1uf capacitors-to-ground. table 10. KSZ8041TL/ftl power pin description
micrel, inc. KSZ8041TL/ftl april 2007 32 m9999-042707-1.1 100base-fx fiber operation (ksz8041ftl only) 100base-fx fiber operation is similar to 100base-tx copper operation with the differences being that the scrambler/de- scrambler and mlt3 encoder/decoder are bypassed on transm ission and reception. in addition, auto-negotiation is bypassed, auto mdi/mdi-x is disabled, and speed is set to 100mbp s. the duplex can be set to either half or full. usually, it is set to full-duplex. fiber signal detect in 100base-fx operation, fxsd (fiber signal detect), input pin 48, is usually connected to the fiber transceiver sd (signal detect) output pin. 100base-fx mode is activated when the fxsd input pin is greater than 1v. when fxsd is between 1v and 1.8v, no fiber signal is detected and a far-end fault is generated. when fxsd is over 2.2v, the fiber signal is detected. 100base-fx mode and signal detection is summarized in the following table: fxsd input voltage mode less than 0.2v copper mode greater than 1v, but le ss than 1.8v fiber mode no signal detected far-end fault generated (if enabled) greater than 2.2v fiber mode signal detected table 11. copper and fiber mode selection to ensure proper operation, a resistive voltage divider is re commended to adjust the fiber transceiver sd (signal detect) output voltage swing to match the fx sd pin?s input voltage threshold. alternatively, the far-end fault feature can be disabled. in this case, the fxsd input pin is tied high to 3.3v to force 100base-fx mode. far-end fault a far-end fault (fef) occurs when the signal detection is logi cally false on the receive side of the fiber transceiver. the ksz8041ftl detects a fef when its fxsd input (pin 48) is between 1v and 1.8v. when a fef is detected, the ksz8041ftl signals its fiber link partner that a fef has occurr ed by transmitting a repetitive pattern of 84-ones and 1- zero. this pattern is used to inform the fiber link part ner that there is a faulty link on its transmit side. by default, fef is enabled. fef is disabled by strapping ?no fef? (pin 43) low. see ?strapping options? section for detail.
micrel, inc. KSZ8041TL/ftl april 2007 33 m9999-042707-1.1 back-to-back media converter a ksz8041ftl and a KSZ8041TL can be connected back-to-back to provide a low cost media converter solution. in back-to-back mode, media conversion is between 100base-fx fiber and 100base-tx copper. on the copper side, link up at 10base-t is not allowed, and is blocked during auto-negotiation. figure 10. ksz8041ftl / KSZ8041TL back-to-back media converter the ksz8041ftl and KSZ8041TL support mii back-to-back mode and rmii back-to-back mode for media conversion. mii back-to-back mode the ksz8041ftl and KSZ8041TL are configured in mii back-to-bac k mode after it is power-up or reset with the following: ? config[2:0] (pins 27, 41, 40) set to ?110? for both ksz8041ftl and KSZ8041TL. ? a common 25 mhz reference clock connected to xi (pin 15) of both ksz8041ftl and KSZ8041TL. ? mii signals connected as shown in the following table between ksz8041ftl in fiber mode and KSZ8041TL in copper mode. ksz8041ftl in fiber mode KSZ8041TL in copper mode pin name pin number pin type pin name pin number pin type rxc 28 output txc 33 input rxdv 27 output txen 34 input rxd3 20 output txd3 39 input rxd2 21 output txd2 38 input rxd1 22 output txd1 36 input rxd0 23 output txd0 35 input txc 33 input rxc 28 output txen 34 input rxdv 27 output txd3 39 input rxd3 20 output txd2 38 input rxd2 21 output txd1 36 input rxd1 22 output txd0 35 input rxd0 23 output table 12. mii signal connection for mii back-to-back mode
micrel, inc. KSZ8041TL/ftl april 2007 34 m9999-042707-1.1 rmii back-to-back mode the ksz8041ftl and KSZ8041TL are configured in rmii back-to -back mode after it is power-up or reset with the following: ? config[2:0] (pins 27, 41, 40) set to ?101? for both ksz8041ftl and KSZ8041TL. ? a common 50 mhz reference clock connected to refclk (pin 15) of both ksz8041ftl and KSZ8041TL. ? rmii signals connected as shown in the following table between ksz8041ftl in fiber mode and KSZ8041TL in copper mode. ksz8041ftl in fiber mode KSZ8041TL in copper mode pin name pin number pin type pin name pin number pin type crsdv 27 output txen 34 input rxd1 22 output txd1 36 input rxd0 23 output txd0 35 input txen 34 input crsdv 27 output txd1 36 input rxd1 22 output txd0 35 input rxd0 23 output table 13. rmii signal connect ion for rmii back-to-back mode rmii back-to-back mode provides the option to disable and tr i-state the transmitter on both copper and fiber sides if the cable is disconnected on the copper side. on the copper side, rx d2 (pin 21) indicates if there is energy detected at the receive inputs of the utp port. rxd2 outputs a low if there is no energy detected (cable disconnected), and outputs a high if there is energy detected (cable connected). the rxd2 output is connected thru an inverter to drive txd2 (pin 38) input high to disable and tri-state the tran smitters for both copper and fiber sides. the txd3 and txd2 pins should be pulled down with 1k re sistors, and rxd3 and rxd2 pins should be left floating, if they are not used.
micrel, inc. KSZ8041TL/ftl april 2007 35 m9999-042707-1.1 register map register number (hex) description 0h basic control 1h basic status 2h phy identifier 1 3h phy identifier 2 4h auto-negotiation advertisement 5h auto-negotiation link partner ability 6h auto-negotiation expansion 7h auto-negotiation next page 8h link partner next page ability 9h ? 14h reserved 15h rxer counter 16h ? 1ah reserved 1bh interrupt control/status 1ch reserved 1dh linkmd ? control/status 1eh phy control 1 1fh phy control 2 register description address name description mode (1) default register 0h ? basic control 0.15 reset 1 = software reset 0 = normal operation this bit is self-cleared after a ?1? is written to it. rw/sc 0 0.14 loop-back 1 = loop-back mode 0 = normal operation rw 0 0.13 speed select (lsb) 1 = 100mbps 0 = 10mbps this bit is ignored if auto-negotiation is enabled (register 0.12 = 1). rw set by speed strapping pin. see ?strapping options? section for details. 0.12 auto- negotiation enable 1 = enable auto-negotiation process 0 = disable auto-negotiation process if enabled, auto-negotiation result overrides settings in register 0.13 and 0.8. rw set by nwayen strapping pin. see ?strapping options? section for details. 0.11 power down 1 = power down mode 0 = normal operation rw 0 0.10 isolate 1 = electrical isolation of phy from mii and tx+/tx- 0 = normal operation rw set by iso strapping pin. see ?strapping options? section for details. 0.9 restart auto- negotiation 1 = restart auto-negotiation process 0 = normal operation. this bit is self-cleared after a ?1? is written to it. rw/sc 0
micrel, inc. KSZ8041TL/ftl april 2007 36 m9999-042707-1.1 address name description mode (1) default 0.8 duplex mode 1 = full-duplex 0 = half-duplex rw set by duplex strapping pin. see ?strapping options? section for details. 0.7 collision test 1 = enable col test 0 = disable col test rw 0 0.6:1 reserved ro 000_000 0.0 disable transmitter 0 = enable transmitter 1 = disable transmitter rw 0 register 1h ? basic status 1.15 100base-t4 1 = t4 capable 0 = not t4 capable ro 0 1.14 100base-tx full duplex 1 = capable of 100mbps full-duplex 0 = not capable of 100mbps full-duplex ro 1 1.13 100base-tx half duplex 1 = capable of 100mbps half-duplex 0 = not capable of 100mbps half-duplex ro 1 1.12 10base-t full duplex 1 = capable of 10mbps full-duplex 0 = not capable of 10mbps full-duplex ro 1 1.11 10base-t half duplex 1 = capable of 10mbps half-duplex 0 = not capable of 10mbps half-duplex ro 1 1.10:7 reserved ro 0000 1.6 no preamble 1 = preamble suppression 0 = normal preamble ro 1 1.5 auto- negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed ro 0 1.4 remote fault 1 = remote fault 0 = no remote fault ro/lh 0 1.3 auto- negotiation ability 1 = capable to perform auto-negotiation 0 = not capable to perform auto-negotiation ro 1 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber detected 0 = jabber not detected (default is low) ro/lh 0 1.0 extended capability 1 = supports extended capabilities registers ro 1 register 2h ? phy identifier 1 2.15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique identifier (oui). kendin communication?s oui is 0010a1 (hex) ro 0022h
micrel, inc. KSZ8041TL/ftl april 2007 37 m9999-042707-1.1 address name description mode (1) default register 3h ? phy identifier 2 3.15:10 phy id number assigned to the 19th through 24 th bits of the organizationally unique identifier (oui). kendin communication?s oui is 0010a1 (hex) ro 0001_01 3.9:4 model number six bit manuf acturer?s model number ro 01_0001 3.3:0 revision number four bit manufacturer?s model number ro 0010 register 4h ? auto-negotiation advertisement 4.15 next page 1 = next page capable 0 = no next page capability. rw 0 4.14 reserved ro 0 4.13 remote fault 1 = remote fault supported 0 = no remote fault rw 0 4.12:11 reserved ro 00 4.10 pause 1 = pause function supported 0 = no pause function supported rw 0 4.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 4.8 100base-tx full-duplex 1 = 100mbps full-duplex capable 0 = no 100mbps full-duplex capability rw set by speed strapping pin. see ?strapping options? section for details. 4.7 100base-tx half-duplex 1 = 100mbps half-duplex capable 0 = no 100mbps half-duplex capability rw set by speed strapping pin. see ?strapping options? section for details. 4.6 10base-t full-duplex 1 = 10mbps full-duplex capable 0 = no 10mbps full-duplex capability rw 1 4.5 10base-t half-duplex 1 = 10mbps half-duplex capable 0 = no 10mbps half-duplex capability rw 1 4.4:0 selector field [0000 1] = ieee 802.3 rw 0_0001 register 5h ? auto-negot iation link partner ability 5.15 next page 1 = next page capable 0 = no next page capability ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected 0 = no remote fault ro 0 5.12 reserved ro 0 5.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric & symmetric pause ro 00
micrel, inc. KSZ8041TL/ftl april 2007 38 m9999-042707-1.1 address name description mode (1) default 5.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 5.8 100base-tx full-duplex 1 = 100mbps full-duplex capable 0 = no 100mbps full-duplex capability ro 0 5.7 100base-tx half-duplex 1 = 100mbps half-duplex capable 0 = no 100mbps half-duplex capability ro 0 5.6 10base-t full-duplex 1 = 10mbps full-duplex capable 0 = no 10mbps full-duplex capability ro 0 5.5 10base-t half-duplex 1 = 10mbps half-duplex capable 0 = no 10mbps half-duplex capability ro 0 5.4:0 selector field [0000 1] = ieee 802.3 ro 0_0001 register 6h ? auto-negotiation expansion 6.15:5 reserved ro 0000_0000_000 6.4 parallel detection fault 1 = fault detected by parallel detection 0 = no fault detected by parallel detection. ro/lh 0 6.3 link partner next page able 1 = link partner has next page capability 0 = link partner does not have next page capability ro 0 6.2 next page able 1 = local device has next page capability 0 = local device does not have next page capability ro 1 6.1 page received 1 = new page received 0 = new page not received yet ro/lh 0 6.0 link partner auto- negotiation able 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation capability ro 0 register 7h ? auto-negotiation next page 7.15 next page 1 = additional next page(s) will follow 0 = last page rw 0 7.14 reserved ro 0 7.13 message page 1 = message page 0 = unformatted page rw 1 7.12 acknowledge2 1 = will comply with message 0 = cannot comply with message rw 0 7.11 toggle 1 = previous value of the transmitted link code word equaled logic one 0 = logic zero ro 0 7.10:0 message field 11-bit wide field to encode 2048 messages rw 000_0000_0001 register 8h ? link partner next page ability 8.15 next page 1 = additional next page(s) will follow 0 = last page ro 0
micrel, inc. KSZ8041TL/ftl april 2007 39 m9999-042707-1.1 address name description mode (1) default 8.14 acknowledge 1 = successful receipt of link word 0 = no successful receipt of link word ro 0 8.13 message page 1 = message page 0 = unformatted page ro 0 8.12 acknowledge2 1 = able to act on the information 0 = not able to act on the information ro 0 8.11 toggle 1 = previous value of transmitted link code word equal to logic zero 0 = previous value of transmitted link code word equal to logic one ro 0 8.10:0 message field ro 000_0000_0000 register 15h ? rxer counter 15.15:0 rxer counter receive error counter for symbol error frames ro/sc 0000h register 1bh ? interrupt control/status 1b.15 jabber interrupt enable 1 = enable jabber interrupt 0 = disable jabber interrupt rw 0 1b.14 receive error interrupt enable 1 = enable receive error interrupt 0 = disable receive error interrupt rw 0 1b.13 page received interrupt enable 1 = enable page received interrupt 0 = disable page received interrupt rw 0 1b.12 parallel detect fault interrupt enable 1 = enable parallel detect fault interrupt 0 = disable parallel detect fault interrupt rw 0 1b.11 link partner acknowledge interrupt enable 1 = enable link partner acknowledge interrupt 0 = disable link partner acknowledge interrupt rw 0 1b.10 link down interrupt enable 1 = enable link down interrupt 0 = disable link down interrupt rw 0 1b.9 remote fault interrupt enable 1 = enable remote fault interrupt 0 = disable remote fault interrupt rw 0 1b.8 link up interrupt enable 1 = enable link up interrupt 0 = disable link up interrupt rw 0 1b.7 jabber interrupt 1 = jabber occurred 0 = jabber did not occurred ro/sc 0 1b.6 receive error interrupt 1 = receive error occurred 0 = receive error did not occurred ro/sc 0 1b.5 page receive interrupt 1 = page receive occurred 0 = page receive did not occurred ro/sc 0 1b.4 parallel detect fault interrupt 1 = parallel detect fault occurred 0 = parallel detect fault did not occurred ro/sc 0
micrel, inc. KSZ8041TL/ftl april 2007 40 m9999-042707-1.1 address name description mode (1) default 1b.3 link partner acknowledge interrupt 1 = link partner acknowledge occurred 0 = link partner acknowledge did not occurred ro/sc 0 1b.2 link down interrupt 1 = link down occurred 0 = link down did not occurred ro/sc 0 1b.1 remote fault interrupt 1 = remote fault occurred 0 = remote fault did not occurred ro/sc 0 1b.0 link up interrupt 1 = link up occurred 0 = link up did not occurred ro/sc 0 register 1dh ? linkmd ? control/status 1d.15 cable diagnostic test enable 1 = enable cable diagnostic test. after test has completed, this bit is self-cleared. 0 = indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. rw/sc 0 1d.14:13 cable diagnostic test result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test has failed ro 00 1d.12:9 reserved 0000 1d.8:0 cable fault counter distance to fault; it?s approximately 0.4m*(cable fault counter value in decimal) ro 0_0000_0000 register 1eh ? phy control 1 1e.15:14 led mode [00] = led1 : speed led0 : link/activity [01] = led1 : activity led0 : link [10] = reserved [11] = reserved rw 00 1e.13 polarity 0 = polarity is not reversed 1 = polarity is reversed ro 1e.12 far-end fault detect 0 = far-end fault not detected 1 = far-end fault detected this bit applies to ksz8041ftl fiber only. ro 0 1e.11 mdi/mdi-x state 0 = mdi 1 = mdi-x ro 1e.10:8 reserved 1e.7 remote loopback 0 = normal mode 1 = remote (analog) loop back is enable rw 0 1e.6:0 reserved
micrel, inc. KSZ8041TL/ftl april 2007 41 m9999-042707-1.1 address name description mode (1) default register 1fh ? phy control 2 1f.15 hp_mdix 0 = micrel auto mdi/mdi-x mode 1 = hp auto mdi/mdi-x mode rw 1 1f.14 mdi/mdi-x select when auto mdi/mdi-x is disabled, 0 = mdi mode transmit on tx+/- (pins 12,11) and receive on rx+/- (pins 10,9) 1 = mdi-x mode transmit on rx+/- (pins 10,9) and receive on tx+/- (pins 12,11) rw 0 1f.13 pairswap disable 1 = disable auto mdi/mdi-x 0 = enable auto mdi/mdi-x rw 0 1f.12 energy detect 1 = presence of signal on rx+/- analog wire pair 0 = no signal detected on rx+/- ro 0 1f.11 force link 1 = force link pass 0 = normal link operation this bit bypasses the control logic and allow transmitter to send pattern even if there is no link. rw 0 1f.10 power saving 1 = enable power saving 0 = disable power saving if power saving mode is enabled and the cable is disconnected, the rxc clock output (in mii mode) is disabled. rxc clock is enabled after the cable is connected and link is established. rw 0 1f.9 interrupt level 1 = interrupt pin active high 0 = interrupt pin active low rw 0 1f.8 enable jabber 1 = enable jabber counter 0 = disable jabber counter rw 1 1f.7 auto- negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed ro 0 1f.6 enable pause (flow control) 1 = flow control capable 0 = no flow control capability ro 0 1f.5 phy isolate 1 = phy in isolate mode 0 = phy in normal operation ro 0 1f.4:2 operation mode indication [000] = still in auto-negotiation [001] = 10base-t half-duplex [010] = 100base-tx half-duplex [011] = reserved [101] = 10base-t full-duplex [110] = 100base-tx full-duplex [111] = reserved ro 000 1f.1 enable sqe test 1 = enable sqe test 0 = disable sqe test rw 0
micrel, inc. KSZ8041TL/ftl april 2007 42 m9999-042707-1.1 address name description mode (1) default 1f.0 disable data scrambling 1 = disable scrambler 0 = enable scrambler rw 0 note: 1. rw = read/write. ro = read only. sc = self-cleared. lh = latch high. ll = latch low.
micrel, inc. KSZ8041TL/ftl april 2007 43 m9999-042707-1.1 absolute maximum ratings (1) supply voltage (v dd_1.8, v dda_1.8, v 1.8_out ) ........................ -0.5v to +2.4v (v ddio_3.3, v dda_3.3 ) ................................... -0.5v to +4.0v input voltage (all input s) ............................... -0.5v to +4.0v output voltage (all outpu ts) .......................... -0.5v to +4.0v lead temperature (solde ring, 10sec .)....................... 260c storage temperature (t s ) ..........................-55c to +150c operating ratings (2) supply voltage (v ddio_3.3, v dda_3.3 ) .......................... +3.135v to +3.465v ambient temperature (t a ) .............................. 0c to +70c maximum junction temperature (t j max) ................. 125c thermal resistance ( ja ) ....................................69.64c/w electrical characteristics (3) symbol parameter condition min typ max units supply current (4) i dd1 100base-tx chip only (no transformer); full-duplex traffic @ 100% utilization 53 ma i dd2 10base-t chip only (no transformer); full-duplex traffic @ 100% utilization 38 ma i dd3 power saving mode ethernet cable disco nnected (reg. 1f.10 = 1) 32 ma i dd4 power down mode software power down (reg. 0.11 = 1) 4 ma ttl inputs v ih input high voltage 2.0 v v il input low voltage 0.8 v i in input current v in = gnd ~ v ddio -10 10 a ttl outputs v oh output high voltage i oh = -4ma 2.4 v v ol output low voltage i ol = 4ma 0.4 v |i oz | output tri-state leakage 10 a 100base-tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 ? termination across differential output 0.95 1.05 v v imb output voltage imbalance 100 ? termination across differential output 2 % t r , t f rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.25 ns overshoot 5 % v set reference voltage of i set 0.65 v output jitter peak-to-peak 0.7 1.4 ns 10base-t transmit (measured differentially after 1:1 transformer) v p peak differential output voltage 100 ? termination across differential output 2.2 2.8 v jitter added peak-to-peak 3.5 ns t r , t f rise/fall time 25 ns 10base-t receive v sq squelch threshold 5mhz square wave 400 mv
micrel, inc. KSZ8041TL/ftl april 2007 44 m9999-042707-1.1 notes: 1. exceeding the absolute maximum rating may damage the device. stresses greater than the absolute maximum rating may cause pe rmanent damage to the device. operation of the device at these or an y other conditions above those specified in the operating section s of this specification is not implied. maximum conditions fo r extended periods may affect reliability. 2. the device is not guaranteed to function outside its operating rating. 3. t a = 25 c. specification for packaged product only. 4. current consumption is for the si ngle 3.3v supply KSZ8041TL/ftl device only, and includes the 1.8v supply voltage (v dd_1.8, v dda_1.8, v 1.8_out ) that is provided by the KSZ8041TL/ftl. the phy port?s transformer c onsumes an additional 45ma @ 3.3v for 100base-tx and 70ma @ 3.3v fo r 10base-t.
micrel, inc. KSZ8041TL/ftl april 2007 45 m9999-042707-1.1 timing diagrams mii sqe timing (10base-t) txc t sqe col t sqep txen t wl t wh t p figure 11. mii sqe timing (10base-t) timing parameter description min typ max unit t p txc period 400 ns t wl txc pulse width low 200 ns t wh txc pulse width high 200 ns t sqe col (sqe) delay after txen de-asserted 2.5 s t sqep col (sqe) pulse duration 1.0 s table 14. mii sqe timing (10base-t) parameters
micrel, inc. KSZ8041TL/ftl april 2007 46 m9999-042707-1.1 mii transmit timing (10base-t) txc t hd2 t su2 txen txd[3:0] t su1 t hd1 crs t crs2 t crs1 t wh t wl t p figure 12. mii transmit timing (10base-t) timing parameter description min typ max unit t p txc period 400 ns t wl txc pulse width low 200 ns t wh txc pulse width high 200 ns t su1 txd[3:0] setup to rising edge of txc 10 ns t su2 txen setup to rising edge of txc 10 ns t hd1 txd[3:0] hold from rising edge of txc 0 ns t hd2 txen hold from rising edge of txc 0 ns t crs1 txen high to crs asserted latency 4 bit time t crs2 txen low to crs de-asserted latency 8 bit time table 15. mii transmit timing (10base-t) parameters
micrel, inc. KSZ8041TL/ftl april 2007 47 m9999-042707-1.1 mii receive timing (10base-t) figure 13. mii receive timing (10base-t) timing parameter description min typ max unit t p rxc period 400 ns t wl rxc pulse width low 200 ns t wh rxc pulse width high 200 ns t od (rxd[3:0], rxer, rxdv) output delay from rising edge of rxc 182 225 ns t rlat crs to (rxd[3:0], rxer, rxdv) latency 6.5 s table 16. mii receive timing (10base-t) parameters
micrel, inc. KSZ8041TL/ftl april 2007 48 m9999-042707-1.1 mii transmit timing (100base-tx) figure 14. mii transmit timing (100base-tx) timing parameter description min typ max unit t p txc period 40 ns t wl txc pulse width low 20 ns t wh txc pulse width high 20 ns t su1 txd[3:0] setup to rising edge of txc 10 ns t su2 txen setup to rising edge of txc 10 ns t hd1 txd[3:0] hold from rising edge of txc 0 ns t hd2 txen hold from rising edge of txc 0 ns t crs1 txen high to crs asserted latency 4 bit time t crs2 txen low to crs de-asserted latency 4 bit time table 17. mii transmit timing (100base-tx) parameters
micrel, inc. KSZ8041TL/ftl april 2007 49 m9999-042707-1.1 mii receive timing (100base-tx) figure 15. mii receive timing (100base-tx) timing parameter description min typ max unit t p rxc period 40 ns t wl rxc pulse width low 20 ns t wh rxc pulse width high 20 ns t od (rxd[3:0], rxer, rxdv) output delay from rising edge of rxc 19 25 ns t rlat crs to (rxd[3:0], rxer, rxdv) latency 1 2 3 bit time table 18. mii receive timing (100base-tx) parameters
micrel, inc. KSZ8041TL/ftl april 2007 50 m9999-042707-1.1 rmii timing refclk tcyc tx_en txd[1:0] t1 t2 transmit timing figure 16. rmii timing ? data received from rmii refclk tcyc tod crsdv rxd[1:0] receive timing figure 17. rmii timing ? data input to rmii timing parameter description min typ max unit t cyc clock cycle 20 ns t 1 setup time 4 ns t 2 hold time 2 ns t od output delay 2.8 10 ns table 19. rmii timing parameters
micrel, inc. KSZ8041TL/ftl april 2007 51 m9999-042707-1.1 auto-negotiation timing auto-negotiation fast link pulse (flp) timing t pw tx+/tx- clock pulse data pulse clock pulse t pw t ctd t ctc t flpw t btb tx+/tx- data pulse flp burst flp burst figure 18. auto-negotiation fast link pulse (flp) timing timing parameter description min typ max units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulse per flp burst 17 33 table 20. auto-negotiation fast link pulse (flp) timing parameters
micrel, inc. KSZ8041TL/ftl april 2007 52 m9999-042707-1.1 mdc/mdio timing t md1 valid data mdio (phy input) valid data mdc t md2 mdio (phy output) valid data t md3 t p figure 19. mdc/mdio timing timing parameter description min typ max unit t p mdc period 400 ns t 1md1 mdio (phy input) setup to rising edge of mdc 10 ns t md2 mdio (phy input) hold from rising edge of mdc 10 ns t md3 mdio (phy output) delay from rising edge of mdc 222 ns table 21. mdc/mdio timing parameters
micrel, inc. KSZ8041TL/ftl april 2007 53 m9999-042707-1.1 reset timing the KSZ8041TL/ftl reset timing requirement is summarized in the following figure and table. tsr tcs tch trc supply voltage rst# strap-in value strap-in / output pin figure 20. reset timing parameter description min max units t sr stable supply voltage to reset high 10 ms t cs configuration setup time 5 ns t ch configuration hold time 5 ns t rc reset to strap-in pin output 6 ns table 22. reset timing parameters after the de-assertion of reset, it is recommended to wait a minimum of 100s before st arting programming on the miim (mdc/mdio) interface.
micrel, inc. KSZ8041TL/ftl april 2007 54 m9999-042707-1.1 reset circuit the following reset circuit is recommended for powering up the KSZ8041TL/ftl if reset is triggered by the power supply. KSZ8041TL/ftl 3.3v d1 d1: 1n4148 r 10k c 10uf rst# figure 21. recommended reset circuit the following reset circuit is recommended for applications w here reset is driven by another device (e.g., cpu or fpga). at power-on-reset, r, c and d1 provide the necessary ramp rise time to reset the KSZ8041TL/ftl device. the rst_out_n from cpu/fpga provides the warm reset after power up. KSZ8041TL/ftl cpu/fpga 3.3v c 10uf r 10k rst_out_n d1 d2 d1, d2: 1n4148 rst# figure 22. recommended reset circuit for interfacing with cpu/fpga reset output
micrel, inc. KSZ8041TL/ftl april 2007 55 m9999-042707-1.1 the following figure shows the reference circuits for pull- up, float and pull-down on the led1 and led0 strapping pins. led pin 3.3v pull-up KSZ8041TL/ftl 3.3v float KSZ8041TL/ftl led pin 3.3v pull-down KSZ8041TL/ftl led pin figure 23. reference circuits for led strapping pins
micrel, inc. KSZ8041TL/ftl april 2007 56 m9999-042707-1.1 selection of isolation transformer a 1:1 isolation transformer is required at the line interface. an isolation transformer with integrated common-mode chokes is recommended for exceeding fcc requirements. the following table gives recommended transformer characteristics. parameter value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min.) 350 h 100mv, 100khz, 8ma leakage inductance (max.) 0.4 h 1mhz (min.) inter-winding capacitance (max.) 12pf d.c. resistance (max.) 0.9 ? insertion loss (max.) 1.0db 0mhz ? 65mhz hipot (min.) 1500vrms table 23. transformer selection criteria magnetic manufacturer part number auto mdi-x number of port bel fuse s558-5999-u7 yes 1 bel fuse (mag jack) si-46001 yes 1 bel fuse (mag jack) si-50170 yes 1 delta lf8505 yes 1 lankom lf-h41s yes 1 pulse h1102 yes 1 pulse (low cost) h1260 yes 1 transpower hb726 yes 1 tdk (mag jack) tla-6t718 yes 1 table 24. qualified single port magnetics selection of reference crystal characteristics value units frequency 25 mhz frequency tolerance (max) 50 ppm load capacitance (max) 20 pf series resistance 40 ? table 25. typical reference crystal characteristics
micrel, inc. KSZ8041TL/ftl april 2007 57 m9999-042707-1.1 package information , s n o i s u r t o r p r o h s a l f d l o m e d u l c n i t o n s e o d n o i s n e m i d . m m 4 5 2 . 0 d e e c x e t o n l l a h s h c i h w f o r e h t i e . n o i s u r t o r p r a b m a d e d u l c n i t o n s e o d n o i s n e m i d d a e l m o t t o b n a h t r e l l a m s e r a s n o i s n e m i d d l o m p o t e g a k c a p g n a h r e v o t o n l l i w e g a k c a p f o p o t d n a s n o i s n e m i d d l o m . e g a k c a p f o m o t t o b : s e t o n . 1 . 2 . 3 . 4 48-pin (7mm x 7mm) tqfp package note: all dimensions are in millimeters.
micrel, inc. KSZ8041TL/ftl april 2007 58 m9999-042707-1.1 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specific ations at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a si gnificant injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk a nd purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2007 micrel, incor p orated.

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